1. Field
Embodiments of the present invention relate to a lithographic apparatus, an alignment system, e.g. for use in a lithographic apparatus, and a method for manufacturing a device.
2. Background
A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g., including part of one or several dies) on a substrate (e.g., a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
In a typical manufacturing process using a lithographic projection apparatus, a pattern (e.g., in a mask) is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4.
The ever present demand in lithography to be able to image mask patterns with ever decreasing critical dimension (CD) necessitates increasing overlay accuracy (the accuracy with which two successive layers can be aligned with respect to each other). This drives a need for ever increasing alignment accuracy. Since the overlay error must be much smaller than the critical dimension and the alignment error is not the only contribution to overlay error, a critical dimension of 90 nm demands an alignment accuracy of 10 nm or less.
An important step in a typical lithographic process is aligning the substrate to the lithographic apparatus so that the image of the mask pattern is projected at the correct position on the substrate. Semiconductor, and other, devices manufactured by lithographic techniques may require multiple exposures to form multiple layers in the device, and it may be essential that these layers line up correctly. As ever smaller features are imaged, overlay requirements, and hence the accuracy required of the alignment process, become stricter.
In one known alignment system, described in EP-A-0 906 590, which document is hereby incorporated by reference in its entirety, marks on the substrate include two pairs of reference gratings, one X and one Y, with the two gratings of the pair having slightly different periods. The gratings are illuminated with spatially coherent light and the diffracted light is collected and imaged on a detector array, the different diffraction orders having been separated so that corresponding positive and negative orders interfere. Each detector in the array includes a reference grating and a photo detector. As the substrate is scanned, the output of the detector varies sinusoidally. When the signals from both gratings of a pair peak simultaneously, the mark is aligned. This type of system provides a large dynamic range and by using high diffraction orders, is relatively insensitive to mark asymmetry. However, the need to provide two gratings with different periods increases the amount of space required for the alignment marks on the substrate. It is desirable to minimize the amount of such “silicon real estate” devoted to alignment marks and therefore not available for production of devices, or for other purposes.
Another known alignment system, described in EP-A-1 148 390, which document is hereby incorporated by reference in its entirety, uses a compact self-referencing interferometer to generate two overlapping images rotated by +90° and −90° which are then made to interfere in a pupil plane. An optical system and (optional) spatial filter selects and separates the first order beams and re-images them on a detector. The system described in EP-A-1 148 390 utilizes a special technique, also described as self-referencing to determine the center of symmetry of an alignment mark. Also, this alignment system only uses the envelope of the detected signal to determine the correct alignment position.
The following descriptions are intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set out below.